(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of performing Lightly Doped Drain (LDD) implants for High Voltage (HV) and for Low Voltage (LV) polysilicon gate electrodes using one processing sequence thereby enabling the creation of devices that contain both HV and LV polysilicon gate electrodes.
(2) Description of the Prior Art
The continuing striving of the semiconductor industry to reduce device manufacturing costs has been accompanied by a simultaneous emphasis on improving device performance. These objectives have been met in the industry by the continued improvements of a number of interrelated technical disciplines. Key among these disciplines are photolithography and the innovative application of materials combined with new methods of applying processing parameters and processing sequences that are used to create the device features and semiconductor devices. Critical to device performance improvements is the reduction of device dimensions. As an example, the performance of typical Metal Oxide Field Effect Transistors (MOSFET) is critically dependent on the dimensions of the gate electrode that is used in the creation of MOSFET devices. This requirement of creating narrow gate features is closely coupled with the process of photolithography that is used in the creation of the gate electrode. The reduction of gate electrode gate size has been made possible by a confluence of improvements in photolithography (allowing for greater image resolution), in improved photoresist material and in the development of high contrast photoresist material.
Improved etching techniques such as Reactive Ion Etching (RIE) have also contributed to the creation of deep sub-micron device features. With improvements in photo-imaging techniques and advancements in exposure methods, the wavelengths of the exposure sources now reach into the Deep Ultra Violet range. Special techniques such as the application of special layers of material further improve focusing depth and sharpness of focus in creating images in for instance layers of photoresist that are applied to create interconnect lines, vias, contact openings and the like. These techniques are equally applied in the formation of for instance Complementary Metal Oxide Semiconductor (CMOS) devices.
The technique of creating complementary n-channel and p-channel devices has long been known and applied in the semiconductor industry. The salient advantage of these devices is their low power usage due to the fact that two transistors are paired as complementary n-channel and p-channel transistors whereby in either logic state (on/off) of the device, one of the two transistors is off and negligible current is carried through this transistor. The logic elements of Complementary Metal Oxide devices drain significant amounts of current only at the time that these devices switch from one state to another state. Between these transitions the devices draw very little current resulting in low power dissipation for the CMOS device.
The invention addresses an improved method of concurrently creating Lightly Doped Drain (LDD) regions in both high voltage and low voltage CMOS devices, following will therefore be a brief overview of present methods of forming these devices.
A typical n-channel transistor for a CMOS inverter is formed by first forming a p-region (also called tub or well) in the surface of an n-type silicon substrate. Referring to FIG. 1a, there is shown a cross section of a typical MOS transistor that is formed on the surface of a silicon substrate 10. A layer 12 of gate oxide is first formed over the surface of the substrate 10, this layer 12 of oxide serves as a stress relieve layer between the gate of the MOS transistor and the silicon surface. A layer of polysilicon or the like is deposited over the layer of gate oxide 12 and patterned and etched to form the structure 14 of the gate electrode. Source and drain regions (16 and 18 respectively) are then formed self-aligned with and adjacent to the gate electrode 14 by implanting of high-concentration n-type impurities into the surface of the silicon substrate 10. In the era of ULSI devices, the width of the gate has been reduced to below 0.5 um, the distance between the source and the drain region (the channel length) is correspondingly reduced. This sharp reduction in channel length however leads to a significant increase in the concentration of the electromagnetic field close to drain region 18 where this drain region interfaces with the underlying silicon substrate 10. This sharp increase may lead to leakage current between the drain region 18 and the surrounding silicon of substrate 10. In addition, hot carriers can be created in the silicon of the substrate 10 and can gain sufficient energy to penetrate into the layer of gate oxide 12 underneath the gate structure 14 resulting in impacting the threshold voltage between the gate 14 and the substrate 10. This may lead to current flow between the gate electrode 14 and the underlying substrate 10.
To counteract the increase in the electric field, the art has implemented the formation of Lightly Doped Drain (LDD) regions 20 and 22 that are shown in FIG. 1b. The LDD regions 20 and 22 form double off-set regions whereby the source and drain regions now contain high n-type impurity concentrations 16 and 18 and low n-type impurity concentrations 20 and 22. The principle objective of the LDD regions 20 and 22 is to offset the high concentration of the electric field around the drain region 18. The regions are symmetrically formed around the gate electrode and consist of low-concentrations of n-type impurities 20 and 22. The profile of the implanted regions 20 and 22 indicates that the impurity concentrations in the p-n junction change gradually thereby extending to the source and drain regions to attenuate the electric field.
With the creation of the LDD regions 20 and 22, the breakdown between the drain region 18 and the channel region between the source and the drain region has been eliminated. Hot carriers that could affect the threshold voltage are thereby also eliminated. However, the low concentration regions 20 and 22 form high resistivity regions by their nature of being low concentration impurity regions. Since the current flows between the source and drain regions, the regions 20 and 22 are now parasitic resistances that are connected in series between the source and the drain regions. This lowers the drain current and the n-resistance performance of the transistor thereby reducing the performance of the device. Sidewalls 24 and 26 of the gate electrode structure 14 that have been formed on the surfaces of the low-concentration n-source and drain regions further emphasizing this effect. The high electric field that is in effect around the drain region 18 generates hot carriers, some of these carriers may be injected into the lower portion of the sidewall 26 of the drain region 18. The region of the silicon surface of the n-type impurity 22 becomes depleted of carriers due to the electric field that is created by the hot carriers that have become trapped in the underlying layer of gate oxide 12. This results in an increase of the threshold voltage of the transistor thereby having a negative effect on the drain characteristics and ultimately on the reliability of the transistor.
The CMOS device can be divided into a low voltage transistor with operating voltages of no larger than about six volts or a high voltage transistor with an operating voltage in excess of thirteen volts. Low voltage transistors are generally used at the logic or intermediate stages of signal processing while high voltage transistors are generally used as current drivers and switches or as serving at input and output stages of the integrated circuit.
The doping for the formation of regions 20 and 22 is typically performed after the gate spacers 26 have been formed by the process of annealing. The implant for the LDD regions can be, dependent on device type, be a Low Voltage LDD (LVLDD) or a High Voltage LDD (HVLDD). The polysilicon gate electrode is, as part of the creation of the gate, doped in order to establish the desired level of electrical conductivity. It is a requirement that this doping is evenly distributed throughout the body of the gate electrode, which requires that the thickness of the gate electrode be reduced. This brings with it a reduction of the implant energy that can be used to create the LDD regions since too high an implant energy would result in implanted ions penetrating the gate electrode into the underlying silicon of the substrate thereby having a negative effect on the breakdown voltage of the device and on the device functionality. A gate electrode that is reduced in thickness results in reduced implant energy for the HVLDD which results in shallow implants in the LDD regions which in turn results in low breakdown voltage of the high voltage MOS devices.
Since the above-indicated high voltage transistors and the low voltage transistors operate in conjunction with each other, it is often desirable to fabricate these devices on the same substrate. A characteristic of the high voltage device is however that it requires a channel region between the source and the drain regions of the device that can withstand a relatively high induced electric field without experiencing avalanche breakdown whereby excessive currents are created due to the formation of electron hole pairs by the electric field. The result is that high and low voltage transistors frequently have different internal dimensions and that they are frequently formed using different processing sequences. This has in the past led to the formation of high and low voltage transistors on different chips. Required in the creation of high and low voltage transistors is large breakdown voltages (in excess of 13 volts, suitable for current drivers), low source to drain channel resistance, low ionization, low levels of electrical fields around the various areas of dopant implants and low leakage currents.
In a typical High voltage/Low voltage CMOS transistor configuration, HV NMOS, LV NMOS, HV PMOS and LV PMOS can be created on the surface of a substrate. The fabrication of these devices typically applies multiple processing steps that are required to optimize the electrical parameters of the HV N-channel and the P-channel devices while maintaining the desired performance parameters of the LV CMOS devices. Any reduction or simplification in these processing steps is therefore highly desirable and contributes to making these devices more competitive and more widely used.
The above indicated problems in the fabrication of CMOS transistors leads to a requirement for alternate methods of creating these devices, methods that counteract the shallow high voltage junction and the resulting low breakdown voltages of the high voltage MOS device. This requirement takes on increased urgency for devices with micron and sub-micron device features where the impact of low breakdown voltage is only further emphasized.
U.S. Pat. No. 5,366,916 (Summe et al.) shows a method for a HV device.
U.S. Pat. No. 5,498,554 (Mei) shows a HV Device with high doping at surface and low doping a bottom junction.
U.S. Pat. No. 5,024,960 (Haken) shows a dual LDD submicron CMOS process for making low and high voltage transistors with common gate.
A principle objective of the invention is to provide an improved method for simultaneously creating Lightly Doped Drain (LDD) regions for High Voltage and Low Voltage CMOS gate electrodes.
Another objective of the invention is to offset the effect of shallow junction depth for High Voltage CMOS devices thereby reducing potential problems of low breakdown voltage for High Voltage CMOS devices.
Yet another objective of the invention is to simultaneously achieve high breakdown voltage for CMOS devices having HVLDD regions and shallow low voltage junctions for CMOS devices having LVLDD regions.
In accordance with the objectives of the invention a new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. CMOS generally refers to any integrated circuit in which both N-channel and P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) are used in complementary fashion. The gate electrodes of the invention for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is implanted self-aligned with the HV CMOS gate electrode. A gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is implanted self-aligned with the LV CMOS gate electrode. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.